1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to the formation of a material on a semiconductor structure.
2. Description of the Related Art
Integrated circuits typically comprise a large number of circuit elements, which include, in particular, field effect transistors. In a field effect transistor, a gate electrode can be separated from a channel region by a gate insulation layer that provides an electrical insulation between the gate electrode and the channel region. Adjacent the channel region, a source region and a drain region are formed. The channel region, the source region and the drain region can be formed in semiconductor material, wherein the doping of the channel region is inverse to the doping of the source region and the drain region. Thus, there is a PN transition between the source region and the channel region, and between the channel region and the drain region.
Depending on an electric voltage applied to the gate electrode, the field effect transistor can be switched between an on-state, wherein there is a relatively high electrical conductance between the source region and the drain region, and an off-state, wherein there is a relatively low electrical conductance between the source region and the drain region. Depending on the doping of the channel region, one distinguishes between N-channel transistors, wherein the electrical conductance between the source region and the drain region in the on-state is provided substantially by electrons, and P-channel transistors, wherein the electrical conductance between the source region and the drain region is provided substantially by holes.
In the miniaturization of field effect transistors, specific issues may arise. These issues may include a lowering of the electrical conductance of the channel region. It has been proposed to provide a channel region comprising silicon/germanium for increasing the electrical conductance of the channel region. In particular, silicon/germanium can provide a greater mobility of holes, so that a silicon/germanium channel region can be particularly helpful for increasing the electrical conductance of the channel region of a P-channel transistor.
Further issues that may occur in the miniaturization of field effect transistors may include a dependence of the drive current of the transistor on channel length. The drive current is influenced by a capacity between the gate electrode and the channel region, which, in turn, depends on the thickness and the dielectric constant of the gate insulation layer.
Conventionally, the gate insulation layer has been formed from silicon dioxide. However, at the sizes of field effect transistors used in current integrated circuits, an extremely small thickness of a gate insulation layer formed from substantially pure silicon dioxide would be required for obtaining an appropriate drive current of the transistors. A very thin gate insulation layer, however, may have issues associated therewith, which include, in particular, leakage currents caused by tunneling of charge carriers through the gate insulation layer.
To avoid such issues, materials having a greater dielectric constant than silicon dioxide (denoted “high-k materials”) can be used in the formation of the gate insulation layer. A relatively high dielectric constant of the gate insulation layer can increase the capacity between the gate electrode and the channel region compared to a gate insulation layer of the same thickness having a lower dielectric constant, so that a greater dielectric constant of the gate insulation layer can allow obtaining a relatively high capacity at a relatively large thickness of the gate insulation layer.
Gate insulation layers comprising a high-k material can include a relatively thin layer of silicon dioxide formed on the silicon/germanium or silicon channel region, and a layer of a high-k material formed on the silicon dioxide layer. The silicon dioxide layer can passivate the surface of the silicon/germanium or silicon channel region, and can reduce the level of interface states compared to a direct deposition of high-k material on the semiconductor material of the channel region.
Field effect transistors comprising gate insulation layers comprising a high-k material as described above, however, may have specific issues associated therewith.
At an interface between the silicon dioxide of the gate insulation layer and the channel region, gate oxide integrity (GOI) defects can occur, which include locations wherein there is a locally reduced breakthrough voltage of the gate insulation layer. GOI defects may increase the likelihood of failure mechanisms such as time dependent dielectric breakdown (TDDP), wherein a dielectric breakdown of the gate insulation layer occurs as a result of a long-time application of a relatively low electric field.
Issues that may occur in field effect transistors having a gate insulation layer comprising a high-k material as described above can also include bias temperature instability (BTI). BTI, which includes negative bias temperature instability (NBTI) in P-channel transistors and positive bias temperature instability (PBTI) in N-channel transistors, can lead to an alteration of the threshold voltage of the transistor over a period of time, which may adversely affect the functionality of an integrated circuit wherein the transistor is provided. Defects at the interface between the channel region and the gate insulation layer and/or defects within the gate insulation layer, in particular defects within a silicon dioxide layer in the gate insulation layer, may increase the likelihood of bias temperature instability occurring.
An increase of the thickness of the gate insulation layer and/or the thickness of a portion of the gate insulation layer comprising silicon dioxide may improve gate oxide integrity, in particular with respect to time dependent dielectric breakdown and bias temperature instability. However, an increase of the thickness of the gate insulation layer may adversely affect the capacity between the gate electrode and the channel region, and may lead to an increase of the threshold voltage of a field effect transistor. Thus, the performance of the field effect transistor may be adversely affected, and a violation of specification limits may occur. While some of these issues can be reduced by combining an increased thickness of the silicon dioxide in the gate insulation layer with a nitridation, the nitridation may be associated with a degradation of an integrated circuit device wherein the field effect transistor is provided, and may increase manufacturing costs.
In view of the situation described above, the present disclosure relates to manufacturing techniques that allow improving the quality of a gate insulation layer, in particular the quality of a silicon dioxide in a gate insulation layer that comprises a silicon dioxide layer in addition to a layer of a material having a greater dielectric constant than silicon dioxide, while avoiding or at least reducing the effects of one or more of the issues identified above.
Moreover, the present disclosure relates to manufacturing techniques that allow improving a quality of a material layer whose formation comprises a deposition process and a post-treatment process that is performed after the deposition process, in particular, a post-treatment process that is based on a diffusion of species through material deposited in the deposition process.